Emuloi MOS 6502 -prosessoria

Ajattelin, että jatkan eteenpäin ja lähetän oman toteutukseni. Se ei ole täysin golfiton, mutta se on täysin toteutettu.

• 668 C.-riviä (ei lasketa tyhjiä tai vain kommentteja sisältäviä rivejä)
• Tukee (mielestäni ) kaikki dokumentoimattomat ohjeet.
• Tukee BCD: tä.
• CPU: n kellosyklin ajoitus. (mukaan lukien tiettyjen sivurajakääreiden muutokset)
• Voi suorittaa ohjeet joko yksivaiheisesti tai määrittämällä punkkien määrän.
• Tukee ulkoisen toiminnon kytkemistä kutsuttavaksi jokaisen käskyn jälkeen on toteutettu. Tämä johtui siitä, että se oli alun perin NES-emulaattorille, ja käytin tätä äänen ajoitukseen.

/* Fake6502 CPU emulator core v1.1 ******************* * (c)2011-2013 Mike Chambers * *****************************************************/ #include <stdio.h> #include <stdint.h> //externally supplied functions extern uint8_t read6502(uint16_t address); extern void write6502(uint16_t address, uint8_t value); //6502 defines #define UNDOCUMENTED //when this is defined, undocumented opcodes are handled. //otherwise, they"re simply treated as NOPs. //#define NES_CPU //when this is defined, the binary-coded decimal (BCD) //status flag is not honored by ADC and SBC. the 2A03 //CPU in the Nintendo Entertainment System does not //support BCD operation. #define FLAG_CARRY 0x01 #define FLAG_ZERO 0x02 #define FLAG_INTERRUPT 0x04 #define FLAG_DECIMAL 0x08 #define FLAG_BREAK 0x10 #define FLAG_CONSTANT 0x20 #define FLAG_OVERFLOW 0x40 #define FLAG_SIGN 0x80 #define BASE_STACK 0x100 #define saveaccum(n) a = (uint8_t)((n) & 0x00FF) //flag modifier macros #define setcarry() status |= FLAG_CARRY #define clearcarry() status &= (~FLAG_CARRY) #define setzero() status |= FLAG_ZERO #define clearzero() status &= (~FLAG_ZERO) #define setinterrupt() status |= FLAG_INTERRUPT #define clearinterrupt() status &= (~FLAG_INTERRUPT) #define setdecimal() status |= FLAG_DECIMAL #define cleardecimal() status &= (~FLAG_DECIMAL) #define setoverflow() status |= FLAG_OVERFLOW #define clearoverflow() status &= (~FLAG_OVERFLOW) #define setsign() status |= FLAG_SIGN #define clearsign() status &= (~FLAG_SIGN) //flag calculation macros #define zerocalc(n) {\ if ((n) & 0x00FF) clearzero();\ else setzero();\ } #define signcalc(n) {\ if ((n) & 0x0080) setsign();\ else clearsign();\ } #define carrycalc(n) {\ if ((n) & 0xFF00) setcarry();\ else clearcarry();\ } #define overflowcalc(n, m, o) { /* n = result, m = accumulator, o = memory */ \ if (((n) ^ (uint16_t)(m)) & ((n) ^ (o)) & 0x0080) setoverflow();\ else clearoverflow();\ } //6502 CPU registers uint16_t pc; uint8_t sp, a, x, y, status = FLAG_CONSTANT; //helper variables uint64_t instructions = 0; //keep track of total instructions executed uint32_t clockticks6502 = 0, clockgoal6502 = 0; uint16_t oldpc, ea, reladdr, value, result; uint8_t opcode, oldstatus; //a few general functions used by various other functions void push16(uint16_t pushval) { write6502(BASE_STACK + sp, (pushval >> 8) & 0xFF); write6502(BASE_STACK + ((sp - 1) & 0xFF), pushval & 0xFF); sp -= 2; } void push8(uint8_t pushval) { write6502(BASE_STACK + sp--, pushval); } uint16_t pull16() { uint16_t temp16; temp16 = read6502(BASE_STACK + ((sp + 1) & 0xFF)) | ((uint16_t)read6502(BASE_STACK + ((sp + 2) & 0xFF)) << 8); sp += 2; return(temp16); } uint8_t pull8() { return (read6502(BASE_STACK + ++sp)); } void reset6502() { pc = (uint16_t)read6502(0xFFFC) | ((uint16_t)read6502(0xFFFD) << 8); a = 0; x = 0; y = 0; sp = 0xFD; status |= FLAG_CONSTANT; } static void (*addrtable[256])(); static void (*optable[256])(); uint8_t penaltyop, penaltyaddr; //addressing mode functions, calculates effective addresses static void imp() { //implied } static void acc() { //accumulator } static void imm() { //immediate ea = pc++; } static void zp() { //zero-page ea = (uint16_t)read6502((uint16_t)pc++); } static void zpx() { //zero-page,X ea = ((uint16_t)read6502((uint16_t)pc++) + (uint16_t)x) & 0xFF; //zero-page wraparound } static void zpy() { //zero-page,Y ea = ((uint16_t)read6502((uint16_t)pc++) + (uint16_t)y) & 0xFF; //zero-page wraparound } static void rel() { //relative for branch ops (8-bit immediate value, sign-extended) reladdr = (uint16_t)read6502(pc++); if (reladdr & 0x80) reladdr |= 0xFF00; } static void abso() { //absolute ea = (uint16_t)read6502(pc) | ((uint16_t)read6502(pc+1) << 8); pc += 2; } static void absx() { //absolute,X uint16_t startpage; ea = ((uint16_t)read6502(pc) | ((uint16_t)read6502(pc+1) << 8)); startpage = ea & 0xFF00; ea += (uint16_t)x; if (startpage != (ea & 0xFF00)) { //one cycle penlty for page-crossing on some opcodes penaltyaddr = 1; } pc += 2; } static void absy() { //absolute,Y uint16_t startpage; ea = ((uint16_t)read6502(pc) | ((uint16_t)read6502(pc+1) << 8)); startpage = ea & 0xFF00; ea += (uint16_t)y; if (startpage != (ea & 0xFF00)) { //one cycle penlty for page-crossing on some opcodes penaltyaddr = 1; } pc += 2; } static void ind() { //indirect uint16_t eahelp, eahelp2; eahelp = (uint16_t)read6502(pc) | (uint16_t)((uint16_t)read6502(pc+1) << 8); eahelp2 = (eahelp & 0xFF00) | ((eahelp + 1) & 0x00FF); //replicate 6502 page-boundary wraparound bug ea = (uint16_t)read6502(eahelp) | ((uint16_t)read6502(eahelp2) << 8); pc += 2; } static void indx() { // (indirect,X) uint16_t eahelp; eahelp = (uint16_t)(((uint16_t)read6502(pc++) + (uint16_t)x) & 0xFF); //zero-page wraparound for table pointer ea = (uint16_t)read6502(eahelp & 0x00FF) | ((uint16_t)read6502((eahelp+1) & 0x00FF) << 8); } static void indy() { // (indirect),Y uint16_t eahelp, eahelp2, startpage; eahelp = (uint16_t)read6502(pc++); eahelp2 = (eahelp & 0xFF00) | ((eahelp + 1) & 0x00FF); //zero-page wraparound ea = (uint16_t)read6502(eahelp) | ((uint16_t)read6502(eahelp2) << 8); startpage = ea & 0xFF00; ea += (uint16_t)y; if (startpage != (ea & 0xFF00)) { //one cycle penlty for page-crossing on some opcodes penaltyaddr = 1; } } static uint16_t getvalue() { if (addrtable[opcode] == acc) return((uint16_t)a); else return((uint16_t)read6502(ea)); } static void putvalue(uint16_t saveval) { if (addrtable[opcode] == acc) a = (uint8_t)(saveval & 0x00FF); else write6502(ea, (saveval & 0x00FF)); } //instruction handler functions static void adc() { penaltyop = 1; value = getvalue(); result = (uint16_t)a + value + (uint16_t)(status & FLAG_CARRY); carrycalc(result); zerocalc(result); overflowcalc(result, a, value); signcalc(result); #ifndef NES_CPU if (status & FLAG_DECIMAL) { clearcarry(); if ((a & 0x0F) > 0x09) { a += 0x06; } if ((a & 0xF0) > 0x90) { a += 0x60; setcarry(); } clockticks6502++; } #endif saveaccum(result); } static void and() { penaltyop = 1; value = getvalue(); result = (uint16_t)a & value; zerocalc(result); signcalc(result); saveaccum(result); } static void asl() { value = getvalue(); result = value << 1; carrycalc(result); zerocalc(result); signcalc(result); putvalue(result); } static void bcc() { if ((status & FLAG_CARRY) == 0) { oldpc = pc; pc += reladdr; if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary else clockticks6502++; } } static void bcs() { if ((status & FLAG_CARRY) == FLAG_CARRY) { oldpc = pc; pc += reladdr; if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary else clockticks6502++; } } static void beq() { if ((status & FLAG_ZERO) == FLAG_ZERO) { oldpc = pc; pc += reladdr; if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary else clockticks6502++; } } static void bit() { value = getvalue(); result = (uint16_t)a & value; zerocalc(result); status = (status & 0x3F) | (uint8_t)(value & 0xC0); } static void bmi() { if ((status & FLAG_SIGN) == FLAG_SIGN) { oldpc = pc; pc += reladdr; if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary else clockticks6502++; } } static void bne() { if ((status & FLAG_ZERO) == 0) { oldpc = pc; pc += reladdr; if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary else clockticks6502++; } } static void bpl() { if ((status & FLAG_SIGN) == 0) { oldpc = pc; pc += reladdr; if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary else clockticks6502++; } } static void brk() { pc++; push16(pc); //push next instruction address onto stack push8(status | FLAG_BREAK); //push CPU status to stack setinterrupt(); //set interrupt flag pc = (uint16_t)read6502(0xFFFE) | ((uint16_t)read6502(0xFFFF) << 8); } static void bvc() { if ((status & FLAG_OVERFLOW) == 0) { oldpc = pc; pc += reladdr; if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary else clockticks6502++; } } static void bvs() { if ((status & FLAG_OVERFLOW) == FLAG_OVERFLOW) { oldpc = pc; pc += reladdr; if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary else clockticks6502++; } } static void clc() { clearcarry(); } static void cld() { cleardecimal(); } static void cli() { clearinterrupt(); } static void clv() { clearoverflow(); } static void cmp() { penaltyop = 1; value = getvalue(); result = (uint16_t)a - value; if (a >= (uint8_t)(value & 0x00FF)) setcarry(); else clearcarry(); if (a == (uint8_t)(value & 0x00FF)) setzero(); else clearzero(); signcalc(result); } static void cpx() { value = getvalue(); result = (uint16_t)x - value; if (x >= (uint8_t)(value & 0x00FF)) setcarry(); else clearcarry(); if (x == (uint8_t)(value & 0x00FF)) setzero(); else clearzero(); signcalc(result); } static void cpy() { value = getvalue(); result = (uint16_t)y - value; if (y >= (uint8_t)(value & 0x00FF)) setcarry(); else clearcarry(); if (y == (uint8_t)(value & 0x00FF)) setzero(); else clearzero(); signcalc(result); } static void dec() { value = getvalue(); result = value - 1; zerocalc(result); signcalc(result); putvalue(result); } static void dex() { x--; zerocalc(x); signcalc(x); } static void dey() { y--; zerocalc(y); signcalc(y); } static void eor() { penaltyop = 1; value = getvalue(); result = (uint16_t)a ^ value; zerocalc(result); signcalc(result); saveaccum(result); } static void inc() { value = getvalue(); result = value + 1; zerocalc(result); signcalc(result); putvalue(result); } static void inx() { x++; zerocalc(x); signcalc(x); } static void iny() { y++; zerocalc(y); signcalc(y); } static void jmp() { pc = ea; } static void jsr() { push16(pc - 1); pc = ea; } static void lda() { penaltyop = 1; value = getvalue(); a = (uint8_t)(value & 0x00FF); zerocalc(a); signcalc(a); } static void ldx() { penaltyop = 1; value = getvalue(); x = (uint8_t)(value & 0x00FF); zerocalc(x); signcalc(x); } static void ldy() { penaltyop = 1; value = getvalue(); y = (uint8_t)(value & 0x00FF); zerocalc(y); signcalc(y); } static void lsr() { value = getvalue(); result = value >> 1; if (value & 1) setcarry(); else clearcarry(); zerocalc(result); signcalc(result); putvalue(result); } static void nop() { switch (opcode) { case 0x1C: case 0x3C: case 0x5C: case 0x7C: case 0xDC: case 0xFC: penaltyop = 1; break; } } static void ora() { penaltyop = 1; value = getvalue(); result = (uint16_t)a | value; zerocalc(result); signcalc(result); saveaccum(result); } static void pha() { push8(a); } static void php() { push8(status | FLAG_BREAK); } static void pla() { a = pull8(); zerocalc(a); signcalc(a); } static void plp() { status = pull8() | FLAG_CONSTANT; } static void rol() { value = getvalue(); result = (value << 1) | (status & FLAG_CARRY); carrycalc(result); zerocalc(result); signcalc(result); putvalue(result); } static void ror() { value = getvalue(); result = (value >> 1) | ((status & FLAG_CARRY) << 7); if (value & 1) setcarry(); else clearcarry(); zerocalc(result); signcalc(result); putvalue(result); } static void rti() { status = pull8(); value = pull16(); pc = value; } static void rts() { value = pull16(); pc = value + 1; } static void sbc() { penaltyop = 1; value = getvalue() ^ 0x00FF; result = (uint16_t)a + value + (uint16_t)(status & FLAG_CARRY); carrycalc(result); zerocalc(result); overflowcalc(result, a, value); signcalc(result); #ifndef NES_CPU if (status & FLAG_DECIMAL) { clearcarry(); a -= 0x66; if ((a & 0x0F) > 0x09) { a += 0x06; } if ((a & 0xF0) > 0x90) { a += 0x60; setcarry(); } clockticks6502++; } #endif saveaccum(result); } static void sec() { setcarry(); } static void sed() { setdecimal(); } static void sei() { setinterrupt(); } static void sta() { putvalue(a); } static void stx() { putvalue(x); } static void sty() { putvalue(y); } static void tax() { x = a; zerocalc(x); signcalc(x); } static void tay() { y = a; zerocalc(y); signcalc(y); } static void tsx() { x = sp; zerocalc(x); signcalc(x); } static void txa() { a = x; zerocalc(a); signcalc(a); } static void txs() { sp = x; } static void tya() { a = y; zerocalc(a); signcalc(a); } //undocumented instructions #ifdef UNDOCUMENTED static void lax() { lda(); ldx(); } static void sax() { sta(); stx(); putvalue(a & x); if (penaltyop && penaltyaddr) clockticks6502--; } static void dcp() { dec(); cmp(); if (penaltyop && penaltyaddr) clockticks6502--; } static void isb() { inc(); sbc(); if (penaltyop && penaltyaddr) clockticks6502--; } static void slo() { asl(); ora(); if (penaltyop && penaltyaddr) clockticks6502--; } static void rla() { rol(); and(); if (penaltyop && penaltyaddr) clockticks6502--; } static void sre() { lsr(); eor(); if (penaltyop && penaltyaddr) clockticks6502--; } static void rra() { ror(); adc(); if (penaltyop && penaltyaddr) clockticks6502--; } #else #define lax nop #define sax nop #define dcp nop #define isb nop #define slo nop #define rla nop #define sre nop #define rra nop #endif static void (*addrtable[256])() = { /* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F | */ /* 0 */ imp, indx, imp, indx, zp, zp, zp, zp, imp, imm, acc, imm, abso, abso, abso, abso, /* 0 */ /* 1 */ rel, indy, imp, indy, zpx, zpx, zpx, zpx, imp, absy, imp, absy, absx, absx, absx, absx, /* 1 */ /* 2 */ abso, indx, imp, indx, zp, zp, zp, zp, imp, imm, acc, imm, abso, abso, abso, abso, /* 2 */ /* 3 */ rel, indy, imp, indy, zpx, zpx, zpx, zpx, imp, absy, imp, absy, absx, absx, absx, absx, /* 3 */ /* 4 */ imp, indx, imp, indx, zp, zp, zp, zp, imp, imm, acc, imm, abso, abso, abso, abso, /* 4 */ /* 5 */ rel, indy, imp, indy, zpx, zpx, zpx, zpx, imp, absy, imp, absy, absx, absx, absx, absx, /* 5 */ /* 6 */ imp, indx, imp, indx, zp, zp, zp, zp, imp, imm, acc, imm, ind, abso, abso, abso, /* 6 */ /* 7 */ rel, indy, imp, indy, zpx, zpx, zpx, zpx, imp, absy, imp, absy, absx, absx, absx, absx, /* 7 */ /* 8 */ imm, indx, imm, indx, zp, zp, zp, zp, imp, imm, imp, imm, abso, abso, abso, abso, /* 8 */ /* 9 */ rel, indy, imp, indy, zpx, zpx, zpy, zpy, imp, absy, imp, absy, absx, absx, absy, absy, /* 9 */ /* A */ imm, indx, imm, indx, zp, zp, zp, zp, imp, imm, imp, imm, abso, abso, abso, abso, /* A */ /* B */ rel, indy, imp, indy, zpx, zpx, zpy, zpy, imp, absy, imp, absy, absx, absx, absy, absy, /* B */ /* C */ imm, indx, imm, indx, zp, zp, zp, zp, imp, imm, imp, imm, abso, abso, abso, abso, /* C */ /* D */ rel, indy, imp, indy, zpx, zpx, zpx, zpx, imp, absy, imp, absy, absx, absx, absx, absx, /* D */ /* E */ imm, indx, imm, indx, zp, zp, zp, zp, imp, imm, imp, imm, abso, abso, abso, abso, /* E */ /* F */ rel, indy, imp, indy, zpx, zpx, zpx, zpx, imp, absy, imp, absy, absx, absx, absx, absx /* F */ }; static void (*optable[256])() = { /* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F | */ /* 0 */ brk, ora, nop, slo, nop, ora, asl, slo, php, ora, asl, nop, nop, ora, asl, slo, /* 0 */ /* 1 */ bpl, ora, nop, slo, nop, ora, asl, slo, clc, ora, nop, slo, nop, ora, asl, slo, /* 1 */ /* 2 */ jsr, and, nop, rla, bit, and, rol, rla, plp, and, rol, nop, bit, and, rol, rla, /* 2 */ /* 3 */ bmi, and, nop, rla, nop, and, rol, rla, sec, and, nop, rla, nop, and, rol, rla, /* 3 */ /* 4 */ rti, eor, nop, sre, nop, eor, lsr, sre, pha, eor, lsr, nop, jmp, eor, lsr, sre, /* 4 */ /* 5 */ bvc, eor, nop, sre, nop, eor, lsr, sre, cli, eor, nop, sre, nop, eor, lsr, sre, /* 5 */ /* 6 */ rts, adc, nop, rra, nop, adc, ror, rra, pla, adc, ror, nop, jmp, adc, ror, rra, /* 6 */ /* 7 */ bvs, adc, nop, rra, nop, adc, ror, rra, sei, adc, nop, rra, nop, adc, ror, rra, /* 7 */ /* 8 */ nop, sta, nop, sax, sty, sta, stx, sax, dey, nop, txa, nop, sty, sta, stx, sax, /* 8 */ /* 9 */ bcc, sta, nop, nop, sty, sta, stx, sax, tya, sta, txs, nop, nop, sta, nop, nop, /* 9 */ /* A */ ldy, lda, ldx, lax, ldy, lda, ldx, lax, tay, lda, tax, nop, ldy, lda, ldx, lax, /* A */ /* B */ bcs, lda, nop, lax, ldy, lda, ldx, lax, clv, lda, tsx, lax, ldy, lda, ldx, lax, /* B */ /* C */ cpy, cmp, nop, dcp, cpy, cmp, dec, dcp, iny, cmp, dex, nop, cpy, cmp, dec, dcp, /* C */ /* D */ bne, cmp, nop, dcp, nop, cmp, dec, dcp, cld, cmp, nop, dcp, nop, cmp, dec, dcp, /* D */ /* E */ cpx, sbc, nop, isb, cpx, sbc, inc, isb, inx, sbc, nop, sbc, cpx, sbc, inc, isb, /* E */ /* F */ beq, sbc, nop, isb, nop, sbc, inc, isb, sed, sbc, nop, isb, nop, sbc, inc, isb /* F */ }; static const uint32_t ticktable[256] = { /* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F | */ /* 0 */ 7, 6, 2, 8, 3, 3, 5, 5, 3, 2, 2, 2, 4, 4, 6, 6, /* 0 */ /* 1 */ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7, /* 1 */ /* 2 */ 6, 6, 2, 8, 3, 3, 5, 5, 4, 2, 2, 2, 4, 4, 6, 6, /* 2 */ /* 3 */ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7, /* 3 */ /* 4 */ 6, 6, 2, 8, 3, 3, 5, 5, 3, 2, 2, 2, 3, 4, 6, 6, /* 4 */ /* 5 */ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7, /* 5 */ /* 6 */ 6, 6, 2, 8, 3, 3, 5, 5, 4, 2, 2, 2, 5, 4, 6, 6, /* 6 */ /* 7 */ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7, /* 7 */ /* 8 */ 2, 6, 2, 6, 3, 3, 3, 3, 2, 2, 2, 2, 4, 4, 4, 4, /* 8 */ /* 9 */ 2, 6, 2, 6, 4, 4, 4, 4, 2, 5, 2, 5, 5, 5, 5, 5, /* 9 */ /* A */ 2, 6, 2, 6, 3, 3, 3, 3, 2, 2, 2, 2, 4, 4, 4, 4, /* A */ /* B */ 2, 5, 2, 5, 4, 4, 4, 4, 2, 4, 2, 4, 4, 4, 4, 4, /* B */ /* C */ 2, 6, 2, 8, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 6, 6, /* C */ /* D */ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7, /* D */ /* E */ 2, 6, 2, 8, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 6, 6, /* E */ /* F */ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7 /* F */ }; void nmi6502() { push16(pc); push8(status); status |= FLAG_INTERRUPT; pc = (uint16_t)read6502(0xFFFA) | ((uint16_t)read6502(0xFFFB) << 8); } void irq6502() { push16(pc); push8(status); status |= FLAG_INTERRUPT; pc = (uint16_t)read6502(0xFFFE) | ((uint16_t)read6502(0xFFFF) << 8); } uint8_t callexternal = 0; void (*loopexternal)(); void exec6502(uint32_t tickcount) { clockgoal6502 += tickcount; while (clockticks6502 < clockgoal6502) { opcode = read6502(pc++); penaltyop = 0; penaltyaddr = 0; (*addrtable[opcode])(); (*optable[opcode])(); clockticks6502 += ticktable[opcode]; if (penaltyop && penaltyaddr) clockticks6502++; instructions++; if (callexternal) (*loopexternal)(); } } void step6502() { opcode = read6502(pc++); penaltyop = 0; penaltyaddr = 0; (*addrtable[opcode])(); (*optable[opcode])(); clockticks6502 += ticktable[opcode]; if (penaltyop && penaltyaddr) clockticks6502++; clockgoal6502 = clockticks6502; instructions++; if (callexternal) (*loopexternal)(); } void hookexternal(void *funcptr) { if (funcptr != (void *)NULL) { loopexternal = funcptr; callexternal = 1; } else callexternal = 0; } 

Kommentit

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MOS 6502 -emulaattori Haskellissa. Ominaisuuksiin kuuluu:

• bittitarkka toteutus, mukaan lukien hienovarainen P-rekisterin käsittely ja sivujen kääriminen indeksoinnin ja epäsuoran indeksoinnin aikana
• muisti kartoitettu IO, spinpiirin tunnistuksella (joten isäntäprosessori ei t tappi odottaessasi syötettä)
• keskeytä tunnistus (hyppää / haarautuu itseensä)
• CPU toteutettu tarkalleen 200 rivillä & 6502 merkkiä koodi
• CPU-toteutus on puhdasta valtion monadia

Tämä on jonkin verran golf-d-versio täydellisestä toteutuksesta (jossa on enemmän ominaisuuksia), jonka tein tähän haasteeseen, jonka minä ” ll postitse myöhemmin. Golfista huolimatta koodi on edelleen suoraviivainen. Ainoa tunnettu puuttuva ominaisuus on BCD-tila (tulossa …)

Suorittaa ehBASIC-koodin:

& ghc -O2 -o z6502min -Wall -fwarn-tabs -fno-warn-missing-signatures Z6502.hs [1 of 1] Compiling Main ( Z6502.hs, Z6502.o ) Z6502.hs:173:1: Warning: Defined but not used: `nmi" Z6502.hs:174:1: Warning: Defined but not used: `irq" Linking z6502min ... & ./z6502min ehbasic.bin 6502 EhBASIC [C]old/[W]arm ? Memory size ? 48383 Bytes free Enhanced BASIC 2.22 Ready PRINT "Hello World" Hello World Ready 10 FOR I = 1 TO 10 20 FOR J = 1 TO I 30 PRINT J; 40 NEXT J 50 PRINT 60 NEXT I RUN 1 1 2 1 2 3 1 2 3 4 1 2 3 4 5 1 2 3 4 5 6 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 Ready 

Ja koodi, yhteensä alle 300 riviä:

-- Z6502: a 6502 emulator -- by Mark Lentczner module Main (main) where import Control.Applicative import Control.Monad import Control.Monad.State.Strict import Data.Bits import qualified Data.ByteString as B import Data.List import qualified Data.Vector as V import qualified Data.Vector.Unboxed as VU import Data.Word import System.Environment import System.IO {- === CPU: 200 lines, 6502 characters === -} type Addr = Word16 toAd = fromIntegral :: Int -> Addr addr :: Word8 -> Word8 -> Addr addr lo hi = fromIntegral hi `shiftL` 8 .|. fromIntegral lo lohi ad = (fromIntegral ad, fromIntegral $ ad `shiftR` 8) zeroPage v = addr v 0 index ad idx = ad + fromIntegral (idx :: Word8) relativeAddr ad off = index ad off - if off > 0x7f then 256 else 0 data Page = Missing | ROM !B.ByteString | RAM !(VU.Vector Word8) type Memory = V.Vector Page emptyMemory = V.replicate 256 Missing fetchByte ad mv = case mv V.! hi of ROM bs -> B.index bs lo RAM vs -> vs VU.! lo _ -> 0 where (hi,lo) = fromIntegral ad `divMod` 256 storeByte ad v mv = case mv V.! hi of RAM vs -> mv V.// [(hi, RAM $ vs VU.// [(lo, v)])] _ -> mv where (hi,lo) = fromIntegral ad `divMod` 256 data S = S { rA, rX, rY, rP, rS :: !Word8, rPC :: !Addr , mem :: !Memory, busR,busW :: Maybe Addr } powerOnState = S 0 0 0 0 0 0 emptyMemory Nothing Nothing [bitN, bitV, bitX, bitB, bitD, bitI, bitZ, bitC] = [7,6..0] toBit b t v = (if t then setBit else clearBit) v b toZ v = toBit bitZ (v == 0) toZN v = toBit bitZ (v == 0) . toBit bitN (testBit v 7) to67 v = toBit bitV (testBit v 6) . toBit bitN (testBit v 7) setZN v = modify $ \s -> s { rP = toZN v $ rP s } setAZN v = modify $ \s -> s { rA = v, rP=toZN v $ rP s } setXZN v = modify $ \s -> s { rX = v, rP=toZN v $ rP s } setYZN v = modify $ \s -> s { rY = v, rP=toZN v $ rP s } setZVNbit (a,v) = modify $ \s -> s { rP = toZ (a .&. v) $ to67 v $ rP s } setACZVN (c,v,a) = modify $ \s -> s { rA = a, rP = toBit bitC c $ toBit bitV v $ toZN a $ rP s } setCZN (c,v) = modify $ \s -> s { rP = toBit bitC c $ toZN v $ rP s } fetch a = state $ \s -> (fetchByte a $ mem s, s { busR = Just a }) fetchIndirectAddr a0 = do m <- gets mem let (lo,hi) = lohi a0 a1 = addr (lo+1) hi bLo = fetchByte a0 m bHi = fetchByte a1 m return $ addr bLo bHi store a v = modify $ \s -> s { mem = storeByte a v $ mem s, busW = Just a } clearBus = modify $ \s -> s { busR = Nothing, busW = Nothing } nextPC = state $ \s -> (rPC s, s { rPC = rPC s + 1 }) fetchPC = nextPC >>= \a -> gets mem >>= return . fetchByte a adjSP n m = state $ \s -> (addr (rS s + m) 1, s { rS = rS s + n }) push v = adjSP (-1) 0 >>= flip store v pull = adjSP 1 1 >>= fetch pushAddr a = let (lo, hi) = lohi a in push hi >> push lo pullAddr = addr <$> pull <*> pull pushP fromSW = gets rP >>= push . toBit bitX True . toBit bitB fromSW pullP = pull >>= \v -> modify $ \s -> s { rP = v .&. 0xCF } indexX a = gets rX >>= return . index a indexY a = gets rY >>= return . index a aImm=nextPC aZero=zeroPage<$>fetchPC aZeroX=zeroPage<$>((+)<$>fetchPC<*>gets rX) aZeroY=zeroPage<$>((+)<$>fetchPC<*>gets rY) aRel=flip relativeAddr<$>fetchPC<*>gets rPC aAbs=addr<$>fetchPC<*>fetchPC aAbsX=aAbs>>=indexX aAbsY=aAbs>>=indexY aInd=aAbs>>=fetchIndirectAddr aIndIdx=aZeroX>>=fetchIndirectAddr aIdxInd=aZero>>=fetchIndirectAddr>>=indexY decode = V.fromList $ concat $ transpose [[iBRK,iBPL,iJSR&aAbs,iBMI,iRTI,iBVC,iRTS,iBVS ,iErr,iBCC,iLDY&aImm,iBCS,iCPY&aImm,iBNE,iCPX&aImm,iBEQ] ,cAlu aIndIdx aIdxInd ,cErr//(10,iLDX&aImm) ,cErr ,[iErr,iErr,iBIT&aZero,iErr,iErr,iErr,iErr,iErr ,iSTY&aZero,iSTY&aZeroX,iLDY&aZero,iLDY&aZeroX,iCPY&aZero,iErr,iCPX&aZero,iErr] ,cAlu aZero aZeroX ,cBit aZero aZeroX//(9,iSTX&aZeroY)//(11,iLDX&aZeroY) ,cErr ,[iPHP,iCLC,iPLP,iSEC,iPHA,iCLI,iPLA,iSEI,iDEY,iTYA,iTAY,iCLV,iINY,iCLD,iINX,iSED] ,cAlu aImm aAbsY//(8,iErr) ,[iASLa,iErr,iROLa,iErr,iLSRa,iErr,iRORa,iErr ,iTXA,iTXS,iTAX,iTSX,iDEX,iErr,iNOP,iErr ] ,cErr ,[iErr,iErr,iBIT&aAbs,iErr,iJMP&aAbs,iErr,iJMP&aInd,iErr ,iSTY&aAbs,iErr,iLDY&aAbs,iLDY&aAbsX,iCPY&aAbs,iErr,iCPX&aAbs,iErr] ,cAlu aAbs aAbsX ,cBit aAbs aAbsX//(9,iErr)//(11,iLDX&aAbsY) ,cErr ] cAlt is e o = is >>= (\i->[i&e,i&o]) cAlu = cAlt [iORA,iAND,iEOR,iADC,iSTA,iLDA,iCMP,iSBC] cBit = cAlt [iASL,iROL,iLSR,iROR,iSTX,iLDX,iDEC,iINC] cErr = replicate 16 iErr is//(n,j) = let (f,_:h) = splitAt n is in f++j:h i&a=a>>=i loadIns l a = fetch a >>= l storeIns f a = f >>= store a aluIns set op ad = do v <- fetch ad a <- gets rA set $ op a v modIns op a = fetch a >>= op >>= store a modAccIns op = gets rA >>= op >>= \v -> modify $ \s -> s { rA = v } stIns b op = modify $ \s -> s { rP = op (rP s) b } jump a = modify $ \s -> s { rPC = a } brIns b t = do a <- aRel p <- gets rP when (testBit p b == t) $ jump a adcOp a b cIn = (cOut, v, s) where h = b + (if cIn then 1 else 0) s = a + h cOut = h < b || s < a v = testBit (a `xor` s .&. b `xor` s) 7 sbcOp a b cIn = adcOp a (complement b) cIn carryOp f = gets rP >>= setACZVN . f . flip testBit bitC cmpOp a b = (a >= b, a - b) shiftOp shifter isRot inBit outBit v = do s <- get let newC = testBit v outBit bitIn = toBit inBit $ isRot && testBit (rP s) bitC v" = bitIn $ shifter v 1 put s { rP = toBit bitC newC $ toZN v" $ rP s } return v" vector a = fetchIndirectAddr a >>= jump interrupt isBrk pcOffset a = do gets rPC >>= pushAddr . flip index pcOffset pushP isBrk iSEI vector a reset = vector $ toAd 0xFFFC nmi = interrupt False 0 $ toAd 0xFFFA irq = interrupt False 0 $ toAd 0xFFFE [iORA,iAND,iEOR]=aluIns setAZN<$>[(.|.),(.&.),xor] [iADC,iSBC]=aluIns carryOp<$>[adcOp,sbcOp] iSTA=storeIns$gets rA iLDA=loadIns setAZN iCMP=aluIns setCZN cmpOp [iSTX,iSTY]=storeIns.gets<$>[rX,rY] [iLDX,iLDY]=loadIns<$>[setXZN,setYZN] [iCPX,iCPY]=(\r a->gets r>>= \v->fetch a>>=setCZN.cmpOp v)<$>[rX,rY] [iDEC,iINC]=modIns.(\i v->setZN(v+i)>>return(v+i))<$>[-1,1] [iDEX,iINX]=(gets rX>>=).(setXZN.).(+)<$>[-1,1] [iDEY,iINY]=(gets rY>>=).(setYZN.).(+)<$>[-1,1] shOps=[shiftOp d r b(7-b)|(d,b)<-[(shiftL,0),(shiftR,7)],r<-[False,True]] [iASL,iROL,iLSR,iROR]=modIns<$>shOps [iASLa,iROLa,iLSRa,iRORa]=modAccIns<$>shOps iBIT=aluIns setZVNbit(,) iJMP=jump [iBPL,iBMI,iBVC,iBVS,iBCC,iBCS,iBNE,iBEQ]=brIns<$>[bitN,bitV,bitC,bitZ]<*>[False,True] [iCLC,iSEC,iCLI,iSEI,iCLV,_,iCLD,iSED]=stIns<$>[bitC,bitI,bitV,bitD]<*>[clearBit,setBit] iBRK=interrupt True 1 $ toAd 0xFFFE iJSR a=gets rPC>>=pushAddr.(-1+)>>jump a iRTI=iPLP>>pullAddr>>=jump iRTS=pullAddr>>=jump.(1+) iPHP=pushP True iPLP=pullP iPHA=gets rA>>=push iPLA=pull>>=setAZN iNOP=return () [iTAX,iTAY]=(gets rA>>=)<$>[setXZN,setYZN] [iTXA,iTYA]=(>>=setAZN).gets<$>[rX,rY] iTXS=modify $ \s -> s { rS=rX s } iTSX=gets rS>>=setXZN iErr=gets rPC>>=jump.(-1+) executeOne = clearBus >> fetchPC >>= (decode V.!) . fromIntegral {- === END OF CPU === -} {- === MOTHERBOARD === -} buildMemory rom = loadRAM 0xF0 1 $ loadRAM 0x00 ramSize $ loadROM romStart rom $ emptyMemory where ramSize = 256 - (B.length rom `div` 256) romStart = fromIntegral ramSize loadRAM p0 n = (V.// zip [p0..] (map RAM $ replicate n ramPage)) ramPage = VU.replicate 256 0 loadROM p0 bs = (V.// zip [p0..] (map ROM $ romPages bs)) romPages b = case B.length b of l | l == 0 -> [] | l < 256 -> [b `B.append` B.replicate (256 - l) 0] | l == 256 -> [b] | otherwise -> let (b0,bn) = B.splitAt 256 b in b0 : romPages bn main = getArgs >>= go where go [romFile] = B.readFile romFile >>= exec . buildState . buildMemory go _ = putStrLn "agument should be a single ROM file" buildState m = execState reset (powerOnState { mem = m }) exec s0 = do stopIO <- startIO loop (0 :: Int) s0 stopIO loop n s = do let pcsp = (rPC s, rS s) (n",s") <- processIO n (execState executeOne s) let pcsp" = (rPC s", rS s") if pcsp /= pcsp" then (loop $! n") $! s" else do putStrLn $ "Execution snagged at " ++ show (fst pcsp") startIO = do ibuf <- hGetBuffering stdin obuf <- hGetBuffering stdout iecho <- hGetEcho stdin hSetBuffering stdin NoBuffering hSetBuffering stdout NoBuffering hSetEcho stdin False return $ do hSetEcho stdin iecho hSetBuffering stdin ibuf hSetBuffering stdout obuf putStr "\n\n" processIO n s = do when (busW s == Just outPortAddr) $ do let c = fetchByte outPortAddr $ mem s when (c /= 0) $ hPutChar stdout $ toEnum $ fromIntegral c if (busR s == Just inPortAddr) then do r <- if n < 16 then hWaitForInput stdin 50 else hReady stdin c <- if r then (fromIntegral . fromEnum) <$> hGetChar stdin else return 0 let c" = if c == 0xA then 0xD else c let s" = s { mem = storeByte inPortAddr c" $ mem s } return (0,s") else return (n+1,s) inPortAddr = toAd 0xF004 outPortAddr = toAd 0xF001 

kommentit

• Hyvä työ! Hyvin pieni. En ’ en tunne Haskellia, ehkä minun pitäisi oppia. Rakastan sitä tosiasiaa, että se s 6502 merkkiä. 🙂

Kaikille kiinnostuneille ajattelin, että jaan 6502: n toteutukseni C #: ssä. Kuten muillakin täällä olevilla viesteillä, se on täysin golfiton, mutta on ominaisuuksien täydellinen toteutus.

• Tukee NMOS: ää ja CMOS: ää
• Sisältää useita testiohjelmia, mukaan lukien yllä oleva AllSuite-testi yksikkötesteinä.
• Tukee BCD: tä

Aloitin tämän projektin luomalla ohjeiden laskentataulukon, kun opin ensin suorittimesta. Tajusin, että voisin käyttää tätä laskentataulukkoa säästääni itselleni kirjoittamista. Muutin tämän tekstitiedostotaulukkoon, jonka emulaattori lataa jaksojen laskemisen ja tulosten purkamisen helpottamiseksi.

Koko projekti on saatavana Githubissa = ”3eec727851”>